A complementary metal oxide semiconductor (CMOS) is formed by a p type channel metal oxide semiconductor (PMOS) and an n type channel metal oxide semiconductor (NMOS).
Currently, the low-temperature polysilicon (LTPS) technology is usually adopted to prepare semiconductors of a PMOS area and an NMOS area in a CMOS circuit. As illustrated in FIG. 1, in order to form an array substrate of a PMOS and NMOS circuit, the array substrate comprises a substrate 101, active layers (an active layer 102 of a PMOS transistor and an active layer 102′ of an NMOS transistor), a gate insulating layer 103, gate electrodes (a gate electrode 104 of the PMOS transistor and a gate electrode 104′ of the NMOS transistor), an insulating spacer layer 105 (including a through hole thereon), source and drain electrodes (source and drain electrodes 106 of the PMOS transistor and source and drain electrodes 106′ of the NMOS transistor), a passivation layer 107, a planarization layer 108, a pixel electrode 109 and a pixel define layer 110 in sequence from the bottom up. The process for manufacturing the array substrate by the LTPS technology requires more than five coating processes and 11 masks. The processes of the 11 masks are as follows:
1) Active layer mask;
2) Gate electrode (gate line) mask;
3) P+ doped mask;
4) N+ doped mask;
5) Lightly doped drain (LDD) mask;
6) Through hole mask;
7) Source and drain electrode mask;
8) Passivation layer mask;
9) Planarization layer mask;
10) Pixel electrode (anode) mask;
11) Pixel define layer (PDL) mask.
The above manufacturing process has the defects of complex process and high equipment investment and manufacturing cost.